The present invention relates to integrated circuit packaging, and more particularly, to bypass capacitor pad design and pad via placement on an integrated circuit package.
As the clock frequency and clock signal edge rates of high performance microprocessors and integrated circuits increase, bypass (decoupling) capacitors play an increasingly important role in reducing system noise and suppressing unwanted radiation. To provide an effective bypassing solution, bypass capacitors may need to be placed on both the front side of an integrated circuit package and on the back side of the package directly underneath the die. A capacitor attached under an integrated circuit package is referred to as a land side capacitor (LSC).
FIG. 1 provides a prior-art, simplified edge-view illustration and schematic of bypass LSC 102 attached to integrated circuit package 116 having die 118. Bypass capacitor 102 is shown schematically as a lumped-parameter discrete capacitor connected to Vss pad 104 and Vcc pad 106. Pad 104 is connected to Vss ground plane 108 by via 110 and pad 106 is connected to Vcc power plane 112 by via 114. Pads 104 and 106 are usually of rectangular shape. For simplicity, the entire ground and power planes are not shown, and their connections to die 118 are not shown.
As clock speeds increase to 1 GHz and beyond, and clock signal rise times decrease down into the 100 ps regime, the power delivery design of prior art integrated circuit packages, such as that shown in FIG. 1, may lead to unacceptable loop inductance. Reducing the loop inductance of a power delivery system may reduce the number of required bypass capacitors, as well as increase the system yield, thereby reducing production costs. The present invention is motivated to address these issues.
In one embodiment of the present invention, an integrated circuit package has two pads having interposed digits. Another embodiment of the present invention comprises a package having a first via coupling a first pad to a ground plane, a second via coupling a second pad to a power plane, and a capacitor connected to the first and second pads, where the first and second vias lie underneath the capacitor.